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GLT5160L16
16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
ADVANCED
FEATURES
u Single 3.3 V 0.3 V power supply u Clock frequency 100 MHz / 125 MHz / 143 MHz/ 166 MHz u Fully synchronous operation referenced to clock rising edge u Dual bank operation controlled by BA (Bank Address) u CAS latency- 2 / 3 (programmable) u Burst length- 1 / 2 / 4 / 8 & Full Page (programmable) u Burst type- sequential / interleave (programmable) u Industrial grade available Byte control by DQMU and DQML Column access - random Auto precharge / All bank precharge controlled by A[10] Auto refresh and Self refresh 4096 refresh cycles / 64 ms LVTTL Interface 400-mil, 50-Pin Thin Small Outline Package (TSOP II) with 0.8 mm lead pitch u 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball * pitch & 0.35mm Ball diameter. u u u * u * u u u
GENERAL DESCRIPTION
The GLT5160L16 is a 2-bank x 524288-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The GLT5160L16 achieves very high speed data rate up to 166 MHz, and is suitable for main memory or graphic memory in computer systems.
DEC. 2003 (Rev.2.4)
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FUNCTIONAL BLOCK DIAGRAM
A[10:0] BA CLK CKE CS RAS CAS WE DQML DQMU Control Signal Buffer Address Buffer Mode Register Memory Array Bank #0 I/O Buffer Memory Array Bank #1 DQ[15:0]
Clock Buffer
Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
Signal Description
Signal CLK CKE Type Input Input Description Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When CS is high, any command means No Operation. Combination of RAS, CAS, WE defines basic commands. A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0]. The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command, both banks are precharged. Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one cycle. Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VDDQ and VSSQ are supplied to the Output Buffers only.
CS RAS, CAS, WE A[10:0]
Input Input Input
BA DQ[15:0] DQML
Input Input / Output Input
DQMU
Input
VDD, VSS VDDQ, VSSQ
Power Supply Power Supply
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Control Circuitry
FUNCTIONAL DESCRIPTION
The GLT5160L16 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of RAS, CAS and WE at CLK rising edge. In addition to 3 signals, CS, CKE and A[10] are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK CS RAS CAS WE CKE A[10] Chip Select: L=select, h=deselect ComComComRefresh option @refresh command Precharge Option @ precharge or read/write command Define Basic Com-
Read (READ) [RAS = H, CAS = L, WE = H]
READ command starts burst read from the active bank indicated by BA. First output data appears after CAS latency. When A[10] = H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [RAS = H, CAS =WE = L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A[10] = H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [RAS = L, CAS = H, WE = L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A[10] = H at this command, both banks are deactivated (precharge all, PREA).
Activate (ACT) [RAS = L, CAS = WE = H]
ACT command activates a row in an idle bank indicated by BA.
Auto-Refresh (REFA) [RAS = CAS = L, WE = CKE = H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Any other command should not be asserted until tRC is met.
Command Truth Table [1]
Command Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Mnemonic DESEL NOP ACT PRE PREA WRITE WRITEA READ READA REFA REFS REFSX CKE n1 H H H H H H H H H H H L L Burst Terminate Mode Register Set TBST MRS H H CKE n X X X X X X X X X H L H H X X CS H L L L L L L L L L L H L L L RAS X H L L L H H H H L L X H H L CAS X H H H H L L L L L L X H H L WE X H H L L L L H H H H X H L L BA X X V V V V V V V X X X X X X A[10 ] X X V L H L H L H X X X X X L A[9: 0] X X V X X V V V V X X X X X V
1. H = High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number
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Function Truth Table [1] [2]
Current State IDLE CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L L L L L L WRITE H L L L L L L L L RAS X H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H H L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L X H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X BA BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X BA BA, CA, A[10] BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X BA BA, CA, A[10] BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X BA BA, CA, A[10] BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add Address [3] Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS NOP NOP ILLEGAL [5] ILLEGAL [5] Bank Active, Latch RA NOP [6] Auto-Refresh [7] Mode Register Set [7] NOP NOP NOP Begin Read, Latch CA, Determine AutoPrecharge Begin Write, Latch CA, Determine AutoPrecharge Bank Active / ILLEGAL [5] Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge [8] Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge [8] Bank Active / ILLEGAL [5] Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge [8] Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge [8] Bank Active / ILLEGAL [5] Terminate Burst, Precharge ILLEGAL ILLEGAL Action [4]
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Function Truth Table [1] [2] (Continued)
Current State READ with AUTO PRECHARGE CS H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L PRE -CHARGING H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L RAS X H H H H L L L L X H H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L CAS X H H L L H H L L X H H L L H H L L X H H L H H L L X H H L H H L L X H H L H H L L WE X H L H L H L H L X H L H L H L H L X H L X H L H L X H L X H L H L X H L X H L H L X X X BA, CA, A[10] BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X X BA, CA, A[10] BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X X BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X X BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X X BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add Address [3] Command DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action [4] NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL [5] ILLEGAL [5] ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL [5] ILLEGAL [5] ILLEGAL ILLEGAL NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL [5] ILLEGAL [5] ILLEGAL [5] NOP [6] (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD ) NOP (Row Active after tRCD ) ILLEGAL [5] ILLEGAL [5] ILLEGAL [5] ILLEGAL [5] ILLEGAL ILLEGAL NOP NOP ILLEGAL [5] ILLEGAL [5] ILLEGAL [5] ILLEGAL [5] ILLEGAL ILLEGAL
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Function Truth Table [1] [2] (Continued)
Current State REFRESHING CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L
1. 2. 3. 4. 5. 6. 7. 8.
RAS X H H H L L L L X H H H L L L L
CAS X H H L H H L L X H H L H H L L
WE X H L X H L H L X H L X H L H L X X X
Address [3]
Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS
Action [4] NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add X X X BA, CA, A[10] BA, RA BA, A[10] X Op-Code, Mode-Add
H = High Level, L= Low Level, X = Don't Care. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No OPeration. ILLEGAL = Device operation and/or data-integrity are not guaranteed. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. NOP to bank precharging or in idle state. May precharge bank indicated by BA. ILLEGAL if any bank is not idle. Must satisfy bus contention, bus turn around, write recovery requirements.
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Function Truth Table for CKE [1]
Current State SELF-REFRESH [2] CKE n1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE [3] H H H H H H H L ANY STATE other than listed above H H L L
1. 2. 3. 4.
CKE n X H H H H H L X H L H L L L L L L X H L H L
CS X H L L L L X X X X X L H L L L L X X X X X
RAS X X H H H L X X X X X L X H H H L X X X X X
CAS X X H H L X X X X X X L X H H L X X X X X X
WE X X H L X X X X X X X H X H L X X X X X X X
Add X X X X X X X X X X X X X X X X X X X X X X INVALID
Action
Exit Self-Refresh (Idle after tRC ) Exit Self-Refresh (Idle after tRC ) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle [4] Exit CLK Suspend at Next Cycle [4] Maintain CLK Suspend
H = High Level, L= Low Level, X = Don't Care. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. Must be legal command.
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Power On Sequence
Before starting normal operation, the following power on sequence is necessary to prevent damage or malfunction. 1. Apply power and start clock. Attempt to maintain CKE high, DQMU / DQML high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200 s.
3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after t RP), issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After this sequence, the SDRAM is idle state and ready for normal operation.
SELF REFRESH
REF REFS MODE REGISTER SET
MRS
IDLE
REF
AUTO REFRESH
CKE CKE
CLK SUSPEND
ACT
POWER DOWN
CKE CKE
ROW TBST WRIT WRITE WRITE SUSPEND CKE CKE READE CKE CKE READ SUSPEND TBST REA
WRITE
READ WRITE
READ
WRITE WRITE READE
READE
WRITE A SUSPEND
CKE CKE
WRITE A
READ A
CKE CKE
READ A SUSPEND
PRE PRE PRE
POWER APPLIED
POWER ON
PRE
PRECHARGE Automatic Sequence Command Sequence
Figure 2. Simplified State Diagram
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Mode Register
Burst Length, Burst Type and CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
BA 0
A10 0
A9 WBL
A8 0
A7 O
A6
A5 LTMODE
A4
A3 BT
A2
A1 BL
A0
CLK CS
CL 0 0 LATENC Y MODE 0 0 1 1 1 1 00 01 10 11 00 01 10 11
CAS R R 2 3 R R R R BURST TYPE
0 0 0 0 1 1 1 1
BL 00 01 10 11 00 01 10
BT = 0 1 2 4 8 R R R
BT = 1 1 2 4 8 R R R R
RAS CAS WE BA, A[10:0]
BURST LENGT
1 1 Full Page 0 1
Write Burst Length (WBL) A9 o 1 Length = BL specified Single bit (BL =
SEQUENTIAL INTERLEAVED
CLK CAS Command Address DQ READ Y Q0 Q1 Q2 Q3 Burst Length WRITE Y D0 D1 D2 D3 Burst Length
Burst Type Initial Address A2 0 0 0 0 1 1 1 1 - - - - - - A1 0 0 1 1 0 0 1 1 0 0 1 1 - - A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 4 8 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 B L Sequential 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1
Column Addressing Interleaved 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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OPERATIONAL DESCRIPTION
Bank Activate
The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank address (BA). A row is indicated by the row address A[10:0] The minimum activation interval between one bank and the other bank is tRRD.
Precharge
The PRE command deactivates the bank indicated by BA. When both banks are active, the precharge all command (PREA, PRE + A[10] = H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued.
CLK Command A[9:0] A[10] BA DQ ACT tRRD Xa Xa 0 Xb Xb 1 Ya 0 0 Qa0 Qa1 Qa2 Qa3 1 ACT REA tRAS PRE tRP Xb Xb 1 ACT
Precharge All
Figure 3. Bank Activation and Precharge All (BL=4, CL=3)
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Read
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The start address is specified by A[7:0], and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous output data (in case of BL = 4) by interleaving the dual banks. When A[10] is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge start timing depends on CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing.
CLK Command A[9:0] A[10] BA DQ CAS Latency ACT tRCD Xa Xa 0 Ya 0 0 Xb Xb 1 Qa0 Yb 0 1 0 0 Qa3 Qb0 Qb1 Qb2 REA ACT REA PRE
Burst Length Qa1 Qa2
Figure 4. Dual Bank Interleaving READ (BL=4, CL=3)
CLK Command A[9:0] A[10] BA DQ ACT tRCD Xa Xa 0 Y 1 0 Qa0 Qa1 Qa2 Qa3 READ A tRP Xa Xa 0 ACT
Internal Precharge begins
Figure 5. READ with Auto-Precharge (BL=4, CL=3)
CLK Command CL=3 DQ CL=2 DQ Qa0 ACT READ A Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Internal Precharge Start Timing Qa3
Figure 6. READ Auto-Precharge Timing (BL=4)
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Write
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A[7:0], and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data (in case of BL = 4)
by interleaving the dual banks. From the last input data to the PRE command, the write recovery time (t RDL) is required. When A[10] is high at a WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing.
CLK Command A[9:0] A[10] BA DQ ACT tRCD Xa Xa 0 Y 0 0 Da0 Xb Xb 1 Burst Length Da1 Da2 Da3 WRITE ACT tRCD Y tRDL (1 0 1 Db0 0 0 Db1 Db2 Db3 WRITE PRE
Figure 7. Dual Bank Interleaving WRITE (BL=4)
CLK Command A[9:0] A[10] BA DQ ACT tRCD Xa Xa 0 Y 1 0 tRDL Da0 Da1 Da2 Da3 Internal Precharge Begins WRITE tRP Xa Xa 0 ACT
Figure 8. WRITE with Auto-Precharge (BL=4)
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Burst Interruption
[Read Interrupted by Read]
The burst read operation can be interrupted by a new read of the same or the other bank. GLT5160L16 allows random column access. READ to READ interval is 1 CLK minimum.
CLK Command A[9:0] A[10] BA DQ REA Yi 0 0 REA Yj 0 0 READ Yk 0 1 Qi0 Qj0 Qj1 READ Yl 0 0 Qk0 Qk1 Qk2 Ql0 Ql1 Ql2 Ql3
Internal Precharge Start Timing
Figure 9. READ Interrupted by READ (BL=4, CL=3)
[Read Interrupted by Write]
Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMU / DQML to prevent the bus contention. The output is disabled automatically 2 cycles after WRITE assertion.
CLK Command A[9:0] A[10] BA DQMU, Q D Qi0 DQM U/ DQML control Dj0 Dj1 Dj2 Write control Dj3 REA Yi 0 0 WRITE Yj 0 0
Figure 10. READ Interrupted by WRITE (BL=4, CL=3)
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[Read Interrupted by Precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command disables the data output, depending on the CAS Latency. The figure below shows examples, when the data-out is terminated.
CLK Command DQ CL=3 Command DQ Command DQ Command DQ CL=2 Command DQ Command DQ REA PRE Q0 REA Q0 REA Q0 Q1 PRE Q1 Q2 REA PRE Q0 PRE Q2 Q3 REA REA Q0 PRE Q0 Q1 Q2 PRE Q1 Q2 Q3
Figure 11. READ Interrupted by Precharge (BL=4)
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[Read Interrupted by Burst Terminate]
Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TBST interval is minimum 1 CLK. The figure below shows examples, when the data-out is terminated.
CLK Command DQ CL=3 Command DQ Command DQ Command DQ CL=2 Command DQ Command DQ REA TBST Q0 REA Q0 REA Q0 Q1 TBST Q1 Q2 REA TBST Q0 TBST Q2 Q3 REA REA Q0 TBST Q0 Q1 Q2 TBST Q1 Q2 Q3
Figure 12. READ Interrupted by Burst Terminate (BL=4)
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[Write Interrupted by Write]
Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK.
CLK Command A[9:0] A[10] BA DQ WRIT Yi 0 0 Di0 WRIT Yj 0 0 Dj0 Dj1 WRITE Yk 0 1 Dk0 Dk1 Dk2 WRITE Yl 0 0 Dl0 Dl1 Dl2 Dl3
Figure 13. WRITE Interrupted by WRITE (BL=4)
[Write Interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ
interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". Using the DQMU / DQML to prevent the bus contention is optional.
CLK Command A[9:0] A[10] BA DQMU, DQ Di0 Qj0 Qj1 Dk0 Dk1 Ql0 WRITE Yi 0 0 READ Yj 0 0 WRITE Yk 0 0 READ Yl 0 1
Figure 14. WRITE interrupted by READ (BL=4, CL=3)
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[Write Interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Because the write recovery time (tRDL) is required between the last input data and the next PRE, 3rd data should be masked with DQMU / DQML shown as below.
CLK Command A[9:0] A[10] BA DQMU, DQ Di0 Di1 This data should be masked to satisfy tRDL requirement. WRITE Ya 0 0 0 0 PRE ACT Xb Xb 0
Figure 15. WRITE Interrupted by Precharge (BL=4) [Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. The figure below shows the case 3 words of data are written. Random column access is allowed. WRITE to TBST interval is minimum 1 CLK.
CLK Command A[9:0] A[10] BA DQMU, DQ Da0 Da1 Da2 WRITE Ya 0 0 TBST
Figure 16. WRITE Interrupted by Burst Terminate (BL=4)
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Auto Refresh
Single cycle of auto-refresh is initiated with a REFA (CS = RAS = CAS = L, WE = CKE = H) command. The refresh address is generated internally. 4096 REFA cycles within 64 ms refresh 16 Mbit
memory cells. The auto-refresh is performed on each bank alternately (ping-pong refresh). Before performing an auto-refresh, both banks must be in the idle state. Additional commands must not be supplied to the device before tRC from the REFA command.
CLK CS NOP or Deselect RAS CAS WE CKE A[10:0] BA Auto Refresh on Bank 0 Auto Refresh on Bank 1
Minimum t RC
Figure 17. Auto Refresh
Self Refresh
Self-refresh mode is entered by issuing a REFS command (CS = RAS = CAS = L, WE = H, CKE = L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs including CLK are disabled and ignored, and power consumption due to synchronous inputs is
saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted till then.
CLK Stable CLK CS NOP RAS CAS WE CKE new command A[10:0] minimum tRC for recovery BA Self Refresh Entry Self Refresh Exit 0 X
Figure 18. Self-Refresh
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CLK Suspend
CKE controls the internal CLK at the following cycle. Figure 19 and Figure 20 show how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power
down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored.
ext. CLK CKE int. CLK
CLK CKE Command CKE Command ACT NOP NOP PRE NOP NOP Standby Power Down NOP NOP NOP NOP NOP
Active Power Down NOP NOP NOP NOP NOP
Figure 19. Power Down by CKE
CLK CKE Command DQ WRITE D0 D1 D2 D3 REA Q0 Q1 Q2 Q3
Figure 20. DQ Suspend by CKE
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DQMU / DQML Control
DQMU / DQML is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMU / DQML masks upper / lower input data word by word. DQMU /
DQML to write mask latency is 0. During reads, DQMU / DQML forces upper / lower output to Hi-Z word by word. DQMU / DQML to output Hi-Z latency is 2.
CLK Command DQML DQ[7:0] DQMU DQ[15:8] D0 Masked by DQML = D2 D3 Q0 Q1 Disabled by DQML = Q3 WRITE REA
D0
D1
D3
Q0 Disabled by DQMU
Q2
Q3
Masked by DQMU =
Figure 21. DQMU / DQML Function
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Symbol VDD VDDQ VI VO IO PD TOPR TSTG Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature TA = 25 C comsumer Industrial Storage Temperature Parameter Conditions with respect to VSS with respect to VSSQ with respect to VSS with respect to VSSQ Ratings -1.0 to 4.6 -1.0 to 4.6 -1.0 to 4.6 -1.0 to 4.6 50 1000 0 to 70 -40 to 85 -65 to 150 Unit V V V V mA mW C C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions (T A = 0 to +70C, unless otherwise noted)
Symbol VDD VDDQ VIH [1] VIL [2] Supply Voltage Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs Parameter Min 3.0 3.0 2.0 -0.3 Typ 3.3 3.3 Max 3.6 3.6 VDDQ + 0.3 0.8 Unit V V V V
1. VIH (max) = 5.6 V for pulse width less than 3 ns. 2. VIL (min) = -2.0 V for pulse width less than 3 ns.
DC Characteristics (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0 V, unless otherwise noted)
Symbol VOH VOL IOZ II Parameter High-Level Output Voltage Low-Level Output Voltage Off-state Output Current Input Current Test Conditions IOH = -2 mA IOL = 2 mA Q floating VO = 0 to VDDQ VIH = 0 to V DDQ + 0.3 V -10 -10 Min 2.4 0.4 10 10 Max Unit V V A A
Capacitance (TA = 0 to +70C, V DD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin Input Capacitance, I/O pin VI = VSS f = 1 MHz VI = 25 mVrms Test Condition Min 2.5 2.5 2.5 4 Max 5 5 5 7 Unit pF pF pF pF
G-LINK Technology
DEC. 2003 (Rev.2.4)
21
Average Supply Current from VDD (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V, unless otherwise noted)
Rating (Max) Symbol ICC1S ICC1D ICC2H ICC2L ICC3H ICC3L ICC4 ICC5 ICC6 Parameter Operating Current, Single Bank Operating Current, Dual Bank Standby Current, CKE = H Standby Current, CKE = L Active Standby Current, CKE = H Active Standby Current, CKE = L Burst Current Auto-Refresh Current Self-Refresh Current Test Conditions tRC = min, tCLK = min, BL = 1, CL = 3 tRC = min, tCLK = min, BL = 1, CL = 3 both banks idle, t CLK = min, CKE = H both banks idle, t CLK = min, CKE = L both banks active, tCLK = min, CKE = H both banks active, tCLK = min, CKE = L tCLK = min, BL = 4, CL = 3, both banks active tRC = min, tCLK = min CKE < 0.2 V Low Power -6 120 170 20 2 35 4 180 110 1 500 -7 110 150 20 2 35 4 170 100 1 500 -8 100 140 20 2 35 4 160 90 1 500 -10 90 120 20 2 35 4 140 80 1 500 Unit mA mA mA mA mA mA mA mA mA A
AC Characteristics (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V, unless otherwise noted) [1]
-6 Symbol tCLK tCH tCL tT tIS tIH tRC tRCD tRAS tRP tCCD tRRD tRSC tRDL tREF Parameter CLK Cycle Time CL=2 CL=3 CLK High Pulse Width CLK Low Pulse Width Transition Time of CLK Input Setup Time (all inputs) Input Hold Time (all inputs) Row Cycle Time Row to Column Delay Row Active Time Row Precharge Time Column Address to Column Adress Delay Act to Act Delay Time Mode Register Set Cycle Time Last Data-In to Row Precharge Delay Refresh Interval Time Min 6 2.5 2.5 1 2 1 60 18 42 18 1 2 1 1 65.6 100k 10 Max Min 9 7 3 3 1 2.5 1 63 21 42 21 1 2 1 1 65.6 100k 10 -7 Max Min 10 8 3 3 1 2.5 1 72 24 48 24 1 2 1 1 65.6 100k 10 -8 Max Min 13 10 3.5 3.5 1 2.5 1 90 30 60 30 1 2 1 1 65.6 100k 10 -10 Max Unit ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ms
1. Input Pulse Levels: 0.4 V to 2.4 V with tr/tf = +1/+1 ns. Input Timing Measurement Level: 1.4 V.
CLK
1.4 Any AC timing is referenced to the input signal crossing
Signal
1.4
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
Switching Characteristics (TA = 0 to +70C, VDD = VDDQ = 3.3 0.3 V, VSS = VSSQ = 0 V unless otherwise noted)
-6 Symbol tAC tOH tOLZ tOHZ Parameter Access Time from CL=2 CL=3 Output Hold Time from CLK Delay Time, Output Low Impedance from CLK Delay Time, Output High Impedance from CLK CL=2 CL=3 2.5 1 5.5 Min Max 5.5 2.5 1 7 6 Min -7 Max 7 6 3 1 7 6 Min -8 Max 9 6 3 1 9 7 Min -10 Max 10 7 Unit ns ns ns ns ns ns
CLK VTT = 1.4V tAC 50 VREF = VOUT 50 pF (1) CLK + DQ tOLZ tOH tOHZ
1.4
1.4
1.4 Output Timing Measurement Reference Point
1. For GLT5160L16-6/7, the Output Load is 30
DQ
1.4
Figure 22. Output Load Condition
G-LINK Technology
DEC. 2003 (Rev.2.4)
23
CLK tRCD tRAS CS tRC tRDL tRP
RAS
CAS
WE
CKE
HIG
DQMU,
A[9:0]
Xa
Yi
Xb
A[10]
Xa
Xb
BA
B0
B0
B0
B0
DQ
Di0
Di1
Di2
Di3
ACT
WRITE
PRE
ACT
Figure 23. WRITE Cycle (single bank) BL=4
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
tRDL CLK tRCD tRAS CS tRCD
tRDL
tRRD RAS
tRAS
CAS
WE
CKE
HIG
DQMU,
A[9:0]
Xa
Ya
Xb
Yb
A[10]
Xa
Xb
BA
B0
B0
B1
B
B0
B1
DQ
Da0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
ACT
WRIT
ACT
WRIT
PRE
PRE
Figure 24. WRITE Cycle (Dual Bank) BL=4
G-LINK Technology
DEC. 2003 (Rev.2.4)
25
CLK tRCD tRAS CS tRC tRP
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
Xb
A[10]
Xa
Xb
BA
B0
B0
DQ
Qa0
Qa1
Qa2
Qa3
ACT
READ
PRE
ACT
Figure 25. READ Cycle (Single Bank) BL=4, CL=3
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
tRCD CLK tRRD tRAS CS
tRCD
tRAS tRP
tRC
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
Xb
Yb
Xc
A[10]
Xa
Xb
Xc
BA
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
ACT
READ
ACT
READ
PRE
PRE
ACT
Figure 26. READ Cycle (Dual Bank) BL=4, CL=3
G-LINK Technology
DEC. 2003 (Rev.2.4)
27
CLK tRCD tRAS CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
Yb
A[10]
Xa
BA
DQ
Da0
Da1
Da2
Da3
Qb0
Qb1
Qb2
Qb3
ACT
WRITE
READ
PRE
Figure 27. WRITE to READ (Single Bank) BL=4, CL=3
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
tRCD CLK tRRD tRAS CS
tRCD
tRAS tRP
tWR tRC RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
Xb
Yb
Xc
A[10]
Xa
Xb
Xc
BA
DQ
Da0
Da1
Da2
Da3
Qb0
Qb1
Qb2
Qb3
ACT
WRITE
ACT
REA
PRE
PRE
ACT
Figure 28. WRITE to READ (Dual Bank) BL=4, CL=3
G-LINK Technology
DEC. 2003 (Rev.2.4)
29
CLK tRCD tRAS CS
RAS
CAS
WE
CKE
DQML
DQMU
A[9:0]
Xa
Ya
Yb
A[10]
Xa
BA
DQ[7:0]
Da0
Da2
Da3
Qb0
Qb1
Qb3
DQ[15:8]
Da0
Da1
Da3
Qb0
Qb1
Qb2
ACT
WRITE
READ
PRE
Figure 29. DQM Byte Control for WRITE to READ (Single Bank) BL=4, CL=3
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK tRCD tRAS CS tRDL
RAS
CAS
WE
CKE
for output disable DQMU,
A[9:0]
Xa
Ya
Yb
A[10]
Xa
BA
DQ
Qa0
Qa1
Db0
Db1
Db2
Db3
PRE
READ
WRITE
PRE
Figure 30. READ to WRITE (Single Bank) BL=4, CL=3
G-LINK Technology
DEC. 2003 (Rev.2.4)
31
tRCD CLK tRRD tRAS CS tRC
tRCD
tRAS tRP
tRDL
RAS
CAS
WE
CKE
for output disable DQMU,
A[9:0]
Xa
Ya
Xb
Yb
Xc
A[10]
Xa
Xb
Xc
BA
DQ
Qa0
Qa1
Db0
Db1
Db2
Db3
ACT
READ
ACT
PRE
WRITE
ACT
PRE
Figure 31. READ to WRITE (Dual Bank) BL=4, CL=3
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK tRCD tRC CS tRDL+ t RP
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
Xb
A[10]
Xa
Xb
BA
DQ
Da0
Da1
Da2
Da3
ACT
WRITE
Internal Precharge starts this timing depends on BL
ACT
Figure 32. Write with Auto-Precharge BL=4
G-LINK Technology
DEC. 2003 (Rev.2.4)
33
CLK tRCD tRC CS tRP
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Xa
Ya
Xb
A[10]
Xa
Xb
BA
DQ
Qa0
Qa1
Qa2
Qa3
ACT
READ
Internal Precharge start s @ CL=3, BL=4 this timing depends on CL and BL
ACT
Figure 33. Read with Auto-Precharge BL=4, CL=3
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK tRP tRC
CS
RAS
CAS
WE
CKE
DC High
DQMU,
A[9:0]
A[10]
BA
DQ
PRE
If any bank is active, it must be precharged
REF S
REF
Figure 34. Auto-Refresh
G-LINK Technology
DEC. 2003 (Rev.2.4)
35
CLK tRP
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
A[10]
BA
DQ If any bank is active, it PRE must be precharged
REF S
Figure 35. Self-Refresh Entry
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
CLK tRC NOP or desel CS
RAS
CAS
WE
CKE tSRX
DQMU,
A[9:0]
Xa
A[10]
Xa
BA
DQ
Internal CLK Re-start
ACT
Figure 36. Self-Refresh Exit
G-LINK Technology
DEC. 2003 (Rev.2.4)
37
CLK tRP tRSC tRCD
CS
RAS
CAS
WE
CKE
DQMU,
A[9:0]
Mode
Xa
Ya
A[10]
Xa
BA
DQ
Qa0
Qa1
Qa2
PRE
If any bank is active, it must be precharged
MRS
ACT
READ
Figure 37. Mode Register Set BL=4, CL=3
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
PACKAGING INFORMATION
VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQML WE CAS RAS CS BA A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Top View 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC DQMU CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
Figure 38. 50-Pin 400 mil TSOP II Pin Assignment
1 A B C D E F G H J K L M N P R
VSS
2
DQ15
3
4
5
6
DQ0
7
VDD
DQ14
VSSQ
VDDQ
DQ1
DQ13
VDDQ
VSSQ
DQ2
DQ12
DQ11
DQ4
DQ3
DQ10
VSSQ
VDDQ
DQ5
DQ9
VDDQ
VSSQ
DQ6
DQ8
NC
NC
DQ7
NC
NC
NC
NC
NC
UDQM
LDQM
WE#
NC
CLK
RAS#
CAS#
CKE
NC
NC
CS#
A11
A9
NC
NC
A8
A7
A0
A10
A6
A5
A2
A1
VSS
A4
A3
VDD
Figure 38-1. 60-Ball VFBGA Ball
G-LINK Technology
DEC. 2003 (Rev.2.4)
39
unit : mm
Figure 39. 50-Pin 400 mil Plastic TSOP II Package Dimensions
40
G-LINK Technology
DEC. 2003 (Rev. 2.4)
0.08 M 0.15 M
C C A
A1 CORNER B
0.35~0.40(60X)
7
6
5
4
3
2
1 A B C D E F G
10.10 0.10
9.10
H J K L M N
0.65
P R
0.65 A B 0.15(4X) C C 0.20 0.21 0.04 3.90 6.40 0.10 1.00 MAX SEATING PLANE C 0.27 0.05 0.45 0.03 0.20 C
60-Ball VFBGA ( BOTTOM VIEW )
G-LINK Technology
DEC. 2003 (Rev.2.4)
41
ORDERING INFO
GLT5160L16
Part Number GLT5160L16-10TC GLT5160L16-8TC GLT5160L16-7TC GLT5160L16-6TC GLT5160L16-10FJ GLT5160L16-8FJ GLT5160L16-7FJ GLT5160L16-6FJ GLT5160L16I-10TC GLT5160L16I-8TC GLT5160L16I-7TC GLT5160L16I-6TC GLT5160L16I-10FJ GLT5160L16I-8FJ GLT5160L16I-7FJ GLT5160L16I-6FJ GLT5160L16P-10TC GLT5160L16P-8TC GLT5160L16P-7TC GLT5160L16P-6TC GLT5160L16P-10FJ GLT5160L16P-8FJ GLT5160L16P-7FJ GLT5160L16P-6FJ Mode Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Cycle Time 10 8 7 6 10 8 7 6 10 8 7 6 10 8 7 6 10 8 7 6 10 8 7 6 Max Frequency 100 MHz 125 MHz 143 MHz 166 MHz 100 MHz 125 MHz 143 MHz 166 MHz 100 MHz 125 MHz 143 MHz 166 MHz 100 MHz 125 MHz 143 MHz 166 MHz 100 MHz 125 MHz 143 MHz 166 MHz 100 MHz 125 MHz 143 MHz 166 MHz Interface LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Package 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 50-Pin 400 mil Plastic TSOP II 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
Parts Numbers (Top Mark) Definition :
GLT 5 160 L 16
4 : DRAM 5 : Synchronous DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM 9 : SGRAM
P
SPEED -SRAM
- 7 TC
PACKAGE
T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP(Type I) TC : TSOPll (40/44) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP FG : 48Pin BGA 9x12 FH : 48Pin BGA 8x10 FI : 48Pin BGA 6x8 FJ : 60Ball VFBGA
-SRAM
064 : 8K 256 : 256K 512 : 512K 100 : 1M 200 : 2M 400 : 4M
CONFIG.
04 : x04 08 : x08 16 : x16 32 : x32
-DRAM
10 : 1M(C/EDO) 11 : 1M(C/FPM) 12 : 1M(H/EDO) 13 : 1M(H/FPM) 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) 160 : 16M(EDO) 161 : 16M(FPM) 640 : 64M(EDO) 641 : 64M(FPM)
12 : 12ns 15 : 15ns 20 : 20ns 55 : 55ns 70 : 70ns 85 : 85ns 120 : 120ns
-DRAM VOLTAGE
Blank : 5V L : 3.3V M : 2.5V N : 2.0V 25 : 25ns 28 : 28ns 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns 70 : 70ns 80 : 80ns 100 : 100ns SDRAM : 5 : 5ns/200 MHZ 5.5 : 5.5ns/182 MHZ 6 : 6ns/166 MHZ 7 : 7ns/143 MHZ 8 : 8ns/125 MHZ 10 : 10ns/100 MHZ
-SDRAM
40 : 4M 160 : 16M 320 : 32M,4Bank 640 : 64M
POWER
Blank : Standard L : Low Power LL : Low Low Power SL : Super Low Power
Temperature Range
E : Extended Temperature I : Industrial Temperature Blank : Commercial Temperature P : Pb - free part
G-LINK Technology
DEC. 2003 (Rev.2.4)
43
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G-LINK Technology
DEC. 2003 (Rev. 2.4)
www.glinktech.com
G-LINK Technology 1759 S. Main St., Suite 128 Milpitas, CA 95035 U.S.A. TEL: 408-240-1380 * FAX: 408-240-1385 G-LINK Technology Corporation, Taiwan 6F, No.24-2, Industry E.RD.IV, Science Based Industrial Park, Hsin Chu, Taiwan, R.O.C. TEL: 03-578-2833 * FAX: 03-578-5820
(c) 1998 G-LINK Technology All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of G-LINK Technology. Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given. G-LINK Technology reserves the right to change products or specifications without notice. The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries. G-LINK assumes no liability for G-LINK applications assistance, customer's product design, or infringement of patents arising from use of semiconductor devices in such systems' designs. Nor does G-LINK warrant or represent that any patent right, copyright, or other intellectual property right of G-LINK covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. G-LINK Technology's products are not authorized for use in life support devices or systems. Life support devices or systems are device or systems which are: a) intended for surgical implant into the human body and b) designed to support or sustain life; and when properly used according to label instructions, can reasonably be expected to cause significant injury to the user in the event of failure. The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies.
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